1. Field of the Invention
This invention relates generally to driving signals on a bus, and, more particularly, to a repeater capable of driving a signal onto a plurality of bus segments with only a single clock delay.
2. Description of the Related Art
Generally, computer systems are comprised of a plurality of components, such as processors, memory, interfaces to various peripheral devices, and the like. These components typically communicate with one another via one or more buses. Various driver circuits have been employed to control the generation and detection of signals on these buses. One type of driver circuit that has been commonly employed in high-end computer systems, such as servers, is known as driver transistor logic (DTL).
High-end computer systems, such as servers, tend to be physically large such that the components tend to be spaced significant distances from one another. Thus the buses tend to be physically long, causing significant delays to be experienced by signals delivered over these relatively long distances. Further, these types of systems typically have more components, and thus, more bus segments over which signals must be driven. Both of these factors tend to increase the amount of time it takes to pass a signal over the bus. DTL type circuits have been very successful in these types of systems because they are particularly good at accommodating these significant delays. One aspect of the DTL type circuits that is at least partially responsible for this behavior is that each bus transaction is divided into two parts. That is, signals are delivered onto and retrieved off of the bus over a period of two clock cycles. One advantage that arises out of this two-clock-cycle requirement is that the frequency of the bus may be increased to help data throughput.
One significant disadvantage to DTL type circuits is that they do not scale down well. For example, in less expensive and smaller systems, the components tend to be fewer in number and closer together, and thus, are capable of operating at a substantially faster rate. DTL type circuits, however, remain limited by the two-clock-cycle requirement.